1. Field of the Invention
The present invention is in the field of semiconductor integrated circuit design and, more specifically, pertains to methodologies and design tools for ensuring power integrity in VLSI integrated circuit designs.
2. General Background
An ASIC may have dozens of separate circuit blocks or cores arranged on the chip and interconnected to form a system to meet specific needs. Many such blocks are well defined in advance and made available to the designer "off the shelf" in libraries provided by the ASIC vendor. Other blocks or cores may be licensed from third parties, e.g. a RISC core or DRAM block, while typically additional circuitry is custom designed by the ASIC customer for its specific application. The complete system design, including the power mesh (described below), must provide appropriate voltages to all of these circuit elements.
While ASIC design processes vary from one project to another, they often begin by defining the system at a relatively high level of abstraction, which may be an RTL (register-transfer level) description, for example. Such a description is independent of any specific circuit technology. Even at this level, the designer begins a preliminary layout or "floorplan" of the chip, and forms early estimates of gate count, chip size, power dissipation, pin count, etc. As the system becomes more specifically defined, usually in an HDL like Verilog, more precise estimates of various parameters become available. However, inaccuracies in early estimates can severely impact project budget and schedules. For example, extensive resources expended in simulation and analysis of simulation results can be wasted if the designer is forced to "back up" to revise floorplan or packaging estimates.
One essential requirement of a chip design is that adequate power be provided to all of the circuitry on the chip. The power supply requirements must take into account gate count, clock speeds, switching times, simultaneous switching noise, etc. to ensure proper operation of the system. However, while power supplied to the chip must be adequate it also must be minimized. Power dissipation and related thermal considerations severely limit the power consumption of a chip. These issues are ever more critical as circuit densities, e.g. as reflected in gate count, as well as clock speeds, continue to increase.
Large scale integrated circuits typically have a uniform power/ground distribution "mesh" for distributing power to the various circuits formed on the common substrate or "chip". The uniform power/ground mesh (or simply "power mesh") includes a "power ring"--a low-resistance conductor formed around the periphery of the chip core. Typically several bonding wires connect the power ring to one or more assigned external pins. Inside the power ring, a first series of wires are formed spaced apart in parallel and traversing the ring, for example in the x-direction, while a second series of wires are similarly formed in the y-direction (normal to the x-direction). Generally the first wires are formed in a first metallization layer, while the second (perpendicular) wires are formed in a second metallization layer. Vias with negligible resistance are formed at each intersection between the wires so as to interconnect the metallization layers, thus completing the power mesh. FIG. 1 is a circuit model of a small uniform power/ground distribution network for illustration.
In prior art, the designer obtains or generates a circuit model of the power mesh. A circuit simulation tool, e.g. SPICE, or a general purpose matrix solver is used to analyze the power mesh circuit model. The designer must determine the spatial distribution of voltage drop--sometimes called voltage mapping--as well as lateral current densities of the power supply mesh, in response to the specific current consumption requirements of every circuit element of the design. The prior art methodology (described in greater detail later) applies discrete equations for power integrity analysis. In order to solve the voltage V(x,y) for large mesh sizes, e.g. 0.ltoreq.x.ltoreq.100, 0.ltoreq.y.ltoreq.100, inversion of a matrix with 100*100=10,000 unknowns is necessary. This operation can be very expensive in runtime and therefore prohibitive in RTL floorplanning. As noted above, however, improved estimates of power mesh early in the design process can improve overall design and reduce design cycle time.
It is therefore an object of the present invention to provide efficient estimation of power integrity early in the ASIC design cycle.
A further object of the invention is to provide power integrity information to support optimization and design tradeoffs in the ASIC design process.
Another object of the invention is a practical method of obtaining useful power mesh voltage and lateral current estimates for large power meshes.
Yet another object of the invention is to apply a continuous model of the power mesh to speed up computation in power integrity analysis.
A still further object of the invention is to improve integration of power integrity analysis into the design flow, by reducing runtime, obviating dependency on external software, and reducing memory requirements.
Yet another object of the invention is to provide useful estimates of voltage drop and current densities in an RTL floorplan of an ASIC.
A still further object of the invention is to reduce power integrity analysis response time so as to enable fast, interactive tradeoff between floorplan location and voltage drop at the RTL floorplanning stage.